www.siliconstandard.com 1 of 5 n-channel enhancement-mode power mosfet bv dss 60v r ds(on) 90mw i d 3a the SSM2310GN acheives fast switching performance with low gate charge without a complex drive circuit. it is suitable for low voltage applications such as dc/dc absolute maximum ratings v ds v gs i d i dm p d w/c t stg t j symbol parameter value units r qja maximum thermal resistance, junction-ambient 3 90 c/w symbol parameter value units drain-source voltage 60 v gate-source voltage continuous drain current 3 , t a = 25c 3 a t a = 70c 2.3 a pulsed drain current 1,2 10 a operating junction temperature range -55 to 150 c linear derating factor 0.01 storage temperature range total power dissipation 3 , t a = 25c 1.38 w -55 to 150 c thermal characteristics 20 v pb-free; rohs-compliant sot-23-3 d g s sot-23-3 product summary description ssm23 1 0 gn 10 /16/2005 re v. 3 .1 notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%. 3.mounted on a square inch of copper pad on fr4 board ; 270c/w when mounted on the minimum pad area required for soldering. converters and general load-switching circuits. the SSM2310GN is supplied in an rohs-compliant sot-23-3 package, which is widely used for lower power commercial and industrial surface mount applications.
www.siliconstandard.com 2 of 5 SSM2310GN 10/16/2005 rev.3 .1 electrical characteristics (at tj = 25c, unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 60 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.05 - v/c r ds(on) static drain-source on-resistance v gs =10v, i d =3a - - 90 mw v gs =4.5v, i d =2a - - 120 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =5v, i d =3a - 5 - s i dss drain-source leakage current v ds =60v, v gs =0v - - 10 ua v ds =48v ,v gs =0v , tj = 70c - - 25 ua i gss gate-source leakage current v gs =20v - - 100 na q g total gate charge 2 i d =3a - 6 10 nc q gs gate-source charge v ds =48v - 1.6 - nc q gd gate-drain ("miller") charge v gs =4.5v - 3 - nc t d(on) turn-on delay time 2 v ds =30v - 6 - ns t r rise time i d =1a - 5 - ns t d(off) turn-off delay time r g =3.3w , v gs =10v - 16 - ns t f fall time r d =30w -3- ns c iss input capacitance v gs =0v - 490 780 pf c oss output capacitance v ds =25v - 55 - pf c rss reverse transfer capacitance f=1.0mhz - 40 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward voltage 2 i s =1.2a, v gs =0v - - 1.2 v t rr reverse-recovery time i s =3a, v gs =0v, - 25 - ns q rr reverse-recovery charge di/dt=100a/s - 26 - nc notes: 1.pulse width must be limited to avoid exceeding the maximum junction temperature of 150c. 2.pulse width <300us, duty cycle <2%.
www.siliconstandard.com 3 of 5 ssm23 1 0 gn 10 /16/2005 re v. 3 .1 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristics of fig 6. gate threshold voltage vs. the reverse diode junction temperature 0 2 4 6 8 10 012345 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 10v 7.0v 5.0v 4.5v v g = 3.0 v 0 2 4 6 8 10 012345 v ds , drain-to-source voltage (v) i d , drain current (a) t a = 150 o c 10v 7.0v 5.0v 4.5v v g = 3.0 v 75 81 87 93 99 105 246810 v gs , gate-to-source voltage (v) r ds(on) (m w ) i d =2a t a =25 o c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =3a v g =10v 0 1 2 3 0 0.2 0.4 0.6 0.8 1 1.2 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c 0.4 0.6 0.8 1.0 1.2 1.4 -50 0 50 100 150 t j , junction temperature ( o c) normalized v gs(th) (v)
www.siliconstandard.com 4 of 5 ssm23 1 0 gn 10 /16/2005 re v. 3 .1 fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge 0 2 4 6 8 10 12 14 03691 21 5 q g , total gate charge (nc) v gs , gate to so ur ce voltage (v) i d =3a v ds =30v v ds =38v v ds =48v 10 100 1000 1 5 9 1 31 72 12 52 9 v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized t hermal respo nse (r thja ) 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse p dm duty factor = t/t peak t j = p dm x r thja + t a r thja = 270c/w t t 0.001 0.010 0.100 1.000 10.000 100.000 0.1 1 10 100 1000 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 100us 1ms 10ms 100ms 1s dc
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 5 of 5 ssm23 1 0 gn 10 /16/2005 re v. 3 .1 physical dimensions part marking sot -23-3 millimeters symbol min. max. a 0.89 1.45 a1 0 0.15 a2 0.70 1.30 b 0.30 0.50 c 0.08 0.25 d 2.65 3.10 e 2.10 3.00 e1 1.19 2.30 e 0.95bsc e1 1.90bsc l 0.30 0.60 l1 0.60ref q 0 8 sot-23-3 ndx x part number code: nd = SSM2310GN xx = date/lot code packing: moisture sensitivity level msl3 3000 pcs in antistatic tape on a reel packed in a moisture barrier bag (mbb). *dimensions do not include mold protrusions. for a detailed explanation of these codes, please contact ssc directly.
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